View reviews for professors for this course View On Testudo

ENEE640

Digital CMOS VLSI Design

Review of MOS transistors: fabrication, layout, characterization; CMOS circuit and logic design: circuit and logic simulation, fully complementary CMOS logic, pseudo-nMOS logic, dynamic CMOS logic, pass-transistor logic, clocking strategies; sub system design: ALUs, multipliers, memories, PLAs; architecture design: datapath, floorplanning, iterative cellular arrays, systolic arrays; VLSI algorithms; chip design and test: full custom design of chips, possible chip fabrication by MOSIS and subsequent chip testing.

12 reviews
Average rating: 3.92

Average GPA: 3.81 between 127 students

"W"s are considered to be 0.0 quality points. "Other" grades are not factored into the average GPA calculation.